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Nordic Semiconductor /nrf52805 /PPI /CHENSET

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Interpret as CHENSET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disabled)CH0 0 (Disabled)CH1 0 (Disabled)CH2 0 (Disabled)CH3 0 (Disabled)CH4 0 (Disabled)CH5 0 (Disabled)CH6 0 (Disabled)CH7 0 (Disabled)CH8 0 (Disabled)CH9 0 (Disabled)CH20 0 (Disabled)CH21 0 (Disabled)CH22 0 (Disabled)CH23 0 (Disabled)CH24 0 (Disabled)CH25 0 (Disabled)CH26 0 (Disabled)CH27 0 (Disabled)CH28 0 (Disabled)CH29 0 (Disabled)CH30 0 (Disabled)CH31

CH5=Disabled, CH24=Disabled, CH2=Disabled, CH9=Disabled, CH0=Disabled, CH25=Disabled, CH22=Disabled, CH7=Disabled, CH20=Disabled, CH23=Disabled, CH4=Disabled, CH3=Disabled, CH28=Disabled, CH27=Disabled, CH21=Disabled, CH8=Disabled, CH26=Disabled, CH31=Disabled, CH30=Disabled, CH29=Disabled, CH6=Disabled, CH1=Disabled

Description

Channel enable set register

Fields

CH0

Channel 0 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH1

Channel 1 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH2

Channel 2 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH3

Channel 3 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Enabled): Read: channel enabled

1 (Set): Write: Enable channel
CH4

Channel 4 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH5

Channel 5 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Enabled): Read: channel enabled

1 (Set): Write: Enable channel
CH6

Channel 6 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH7

Channel 7 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH8

Channel 8 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH9

Channel 9 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH20

Channel 20 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH21

Channel 21 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Enabled): Read: channel enabled

1 (Set): Write: Enable channel
CH22

Channel 22 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH23

Channel 23 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH24

Channel 24 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH25

Channel 25 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH26

Channel 26 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH27

Channel 27 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH28

Channel 28 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH29

Channel 29 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH30

Channel 30 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled
CH31

Channel 31 enable set register. Writing ‘0’ has no effect.

0 (Disabled): Read: channel disabled

1 (Set): Write: Enable channel

1 (Enabled): Read: channel enabled

Links

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Register License

Copyright © 2010 - 2021, Nordic Semiconductor ASA All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

  3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data